1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors (NMOS) and/or P-channel transistors (PMOS), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of a NMOS transistor would only be formed above the NMOS transistors. Such selective formation may be accomplished by masking the PMOS transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from above the PMOS transistors. Conversely, for PMOS transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PMOS transistor is formed above the PMOS transistors. The techniques employed in forming such nitride layers with the desired tensile or compressive stress are well known to those skilled in the art.
In a field effect transistor, metal silicide regions are typically formed in the source/drain regions of a transistor to reduce the resistance when a conductive contact is formed to establish electrical connection to the source/drain regions. Such metal silicide regions may be made using a variety of different refractory metals, e.g., nickel, platinum, cobalt, etc., or combinations thereof, and they may be formed using techniques that are well known to those skilled in the art. The typical steps used to form metal silicide regions are: (1) depositing a layer of refractory metal, performing an initial heating process causing the refractory metal to react with underlying silicon containing material; (2) performing an etching process to remove unreacted portions of the layer of refractory metal and (3) performing an additional heating process to form the final phase of the metal silicide. The formation of metal silicide regions is becoming even more important as device dimensions decrease with the associated incorporation of very shallow source/drain regions in advanced devices. More specifically, in newer generation devices is important to accurately control the thickness and location of the metal silicide regions to avoid problems such as so-called spiking and piping whereby electrical short circuits can occur which may lead to reduced device performance or, in a worst case, complete device failure.
The present disclosure is directed to various methods of forming metal silicide regions on semiconductor devices.